A HIGH PERFORMANCE DADDA MULTIPLIER USING 5:2 COMPRESSORS
Author’s Name : A P Gobenath | K Nanthakumar | V Abirami | S Angulakshmi | D Priya | K Sangeetha
Volume 05 Issue 03 Year 2018 ISSN No: 2349-252X Page no: 19-21
In this paper 5:2 Compressor are designed to analyze the Dadda Multiplier based on area, low power consumption and delay. Multiplication is a fundamental operation is most of the signal processing algorithms. Multipliers have large area and high speed operation. To reduction the number stages in dadda multiplier by using 5:2 compressors. The power consumption of the 5:2 compressor is very low by using the exact design of the compressor. The speed of the circuits is high because the delay of the circuit is low compared to 4:2 compressor. To analyze a high speed and low power consumption using the Tanner EDA tool and hardware implementation to be done in FPGA using Xilinx ISE 9.1i.
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