TESTING THE FUNCTIONAL AND MANUFACTURING DEFECTS OF CHIP USING JTAG (&) LABVIEW
Author’s Name : B Hakkem | P Manikanda Prabhu
Volume 05 Issue 01 Year 2018 ISSN No: 2349-252X Page no: 19-22
JTAG is a method for testing interconnects (wire lines) on printed circuit boards or sub-blocks inside an integrated circuit. The effect of testing will affect various parameter of device under test. The statistics which should be observed while testing the circuit such as test coverage, testing time, fault coverage, test vectors, testing power, delay. It is difficult to process the testing with all the criteria into the account. In order to make the process easier
JTAG Protocol, Boundary Scan, IEEE 1149.1 Standard, LabVIEW, RS232, Gates, TAP, PCB
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