IJRE – Volume 5 Issue 1 Paper 6

TESTING THE FUNCTIONAL AND MANUFACTURING DEFECTS OF CHIP USING JTAG (&) LABVIEW

Author’s Name :  B Hakkem | P Manikanda Prabhu

Volume 05 Issue 01  Year 2018  ISSN No:  2349-252X  Page no: 19-22

12

 

 

 

Abstract:

JTAG is a method for testing interconnects (wire lines) on printed circuit boards or sub-blocks inside an integrated circuit. The effect of testing will affect various parameter of device under test. The statistics which should be observed while testing the circuit such as test coverage, testing time, fault coverage, test vectors, testing power, delay. It is difficult to process the testing with all the criteria into the account. In order to make the process easier

Keywords:

JTAG Protocol, Boundary Scan, IEEE 1149.1 Standard, LabVIEW, RS232, Gates, TAP, PCB

References:

  1. Raul Rotar, Flavius Opri?oiu. Department of Automation and Computer Science, Bulevardul Vasile Pârvan, Nr. 2, 300223 Timisoara, jud. Timis, România. Testing Facilities for a Solar Tracking device using Boundary Scan Test Strategies, rotar_raul@hotmail.com ISSN: 2395-0196, Vol . 3, Issue 2, 2017
  2. SALIM A. JAYOUSI, MOHD SAUFEE MUHAMMAD, Department of Electrical and Electronic Engineering, University Malaysia Sarawak, Malaysia” CODE-DRIVEN BOUNDARY SCAN TESTING”. E-mail: sjayousi@qou.edu, msaufee@feng.unimas.my. ISSN: 2320-2084 Volume-3, Issue-1, Jan.-2015
  3. Jutman, A. Sudnitson, R. Ubar Tallinn Technical University, Department of Computer Engineering, Raja 15, 12618 Tallinn, Estonia.” Web-Based Training System for Teaching Principles of Boundary Scan Technique” Email: artur@pld.ttu.ee. 14th EAEEIE conference, Gdansk
  4. Weidong Tang, VLSI Testing ELEC 7250, Boundary Scan Standard Bashar Al-Khalifa, Department of Medical Instrumentation Engineering, Technical College, Iraq. “A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs” Vol. 7, No. 2, April 2010
  5. Brian F., Vivek C., Bing L., Harry L., and Gary K., “IEEE Standard Test Access Port and Boundary Scan Architecture IEEE Std 1149.1- 1990,” Computer Journal of IEEE, vol. 39, no. 2, pp. 195-205, 1990.
  6. Rebaudengo M., Sonza M., and Violante M., “A New Functional Fault Model for FPGA Application Oriented Testing,” in Proceedings of 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Germany, pp. 372-374, 2002.
  7. Raul Rotar: “Automation of Photo voltaic Panels” – Bachelor’s Degree – Coordinator: Conf. Dr. Ing. Valentin Müller, “Aurel Vlaicu” University of Arad, 2015
  8. Tarlochan Kauri; Shraiya Mahajan; Shilpa Verma; Priyanka and Jaimala Gambhir: ”Arduino based Low Cost Active Dual Axis Solar Tracker”, 1st IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems, 2016