LOW POWER AND HIGH SPEED CLOCK DISTRIBUTION USING COARSE-GRAIN POWER GATING TECHNIQUE FOR CLOCK PAIR SHARED FLIP FLOP
Author’s Name : Mohan R | Abirami M
Volume 04 Issue 02 Year 2017 ISSN No: 2349-252X Page no: 11-15
The power savings is maximized by creating a high-fanout physically or electrically symmetric distribution that feeds many CM flip-flop (FF) receivers. Logic signals the FF receivers retain VM compatibility with low-power CMOS logic in the remainder of the chip. This paper presents the first true CM CDN and a new CM pulsed D-type FF where the clock (CLK) input is a CM receiver and the data input (D), an active low enable ,and output (Q) are VM.A new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, a new high-performance current-mode pulsed flip-flop with enable (CMPFFE) using 45 nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 62% lower average power compared to traditional voltage mode clocks. Transistor-based power-gating is implemented by placing sleep transistors in-line between the circuit and the power network or the ground network.
Clock distribution network, cross talk, current-mode, flip-flop, low-power, power gating
- H. Zhang, G. Varghese, and J. M. Rabaey, “Low swing on-chip signaling techniques: Effectiveness and robustness,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8, no. 3, pp. 264–272, Jun. 2000.
- C. Anderson, J. Petrovick, J. Keaty, J. Warnock, G. Nussbaum, J. Tendier, C. Carter, S. Chu, J. Clabes, J.DiLullo, P. Dudley, P. Harvey, B. Krauter, J. LeBlanc, P.-F. Lu, B. McCredie, G. Plum, P. Restle, S. Runyon, M. Scheuermann, S. Schmidt, J. Wagoner, R. Weiss, S. Weitzel, and B. Zoric, “Physical design of a fourth-generation power ghz microprocessor,” in Proc. ISSCC, Feb. 2001, pp. 232–233.
- D. Sylvester and C. Hu, “Analytical modeling and characterization of deep-submicrometer interconnect,” Proc. IEEE, vol. 89, no. 5, pp. 634–664, May 2001.
- A. Katoch, H. Veendrick, and E. Seevinck, “High speed current-mode signaling circuits for on-chip interconnects,” in Proc. ISCAS, May 2005, pp. 4138–4141.
- M. R. Guthaus, G. Wilke, and R. Reis, “Revisiting automated physical synthesis of high-performance clock networks,” ACM Trans. Design Autom. Electron. Syst., vol. 18, no. 2, pp. 31:1–31:27, Apr. 2013.
- M. Yamashina and H. Yamada, “An MOS current mode logic (MCML) circuit for low-power sub-GHz processors,” IEICE Trans. Electron., vol. E75-C, no. 10, pp. 1181–1187, 1992.
- E. Seevinck, P. J. V. Beers, and H. Ontrop, “Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM’s,” J. Solid-State Circuits, vol. 26, no. 4, pp. 525–536, Apr. 1991.
- M. Dave, M. Jain, S. Baghini, and D. Sharma, “A variation tolerant current-mode signaling scheme for on-chip interconnects,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. PP, no. 99, pp. 1–12, Jan. 2012.
- F. Yuan, Cmos Current-Mode Circuits for Data Communications. New York: Springer, Apr. 2007.
- A. Narasimhan, S. Divekar, P. Elakkumanan, and R. Sridhar, “A low power current-mode clock distribution scheme for multi-GHz NoC based SoCs,” in Proc. 18th Int. Conf. VLSI Design, Jan. 2005, pp.130–135.