IMPLEMENTATION OF QUATERNARY LOGIC USING CLOCK BOOSTING TECHNIQUE FOR COMBINATIONAL CIRCUIT
Author’s Name : R. Mohan raj |B. MaheshKumar | C. KrishnaKumar | T. Mani
Volume 03 Issue 01 Year 2016 ISSN No: 2349-252X Page no: 17-21
CMOS (Complementary Metal- Oxide Semiconductor) is a class of integrated circuit in which the term ‘complementary’ refers to the fact, of typical design style with CMOS using p type and n type metal oxide semiconductor field effect transistors for logic functions. CMOS technology is employed in microprocessor, microcontroller, static RAM and other digital logic circuits. Two major characteristics of CMOS device are high noise immunity and low static power consumption. Interconnections play an important role in delay, power and area. Hence interconnection reduction is a major concern in system integration, because it increases the area, power and delay. In this project, Quaternary lookup table and clock boosting techniques are used. The clock boosting technique is to optimize the resistance and power consumption. We design a combinational circuit using the tanner and micro wind software, simulated in a standard 120nm CMOS technology, which is able to function at 120MHz consuming 120µW. The experimental results demonstrate the correct quaternary operation and confirm the power efficiency of the proposed design.
full subtractor, vigor, area
- D. Brito, J. Fernandes, P. Flores, and J. Monteiro, “Design and characterization of a QLUT in a standard CMOS process,” in Proc. IEEE 19th ICECS, Dec. 2012, pp. 288–291.
- R. Cunha, H. Boudinov, and L. Carro, “Quaternary look-up tables using voltage-mode CMOS logic design,” in Proc. 37th Int. Symp. Multiple-Valued Logic, 2007, pp. 56–58.
- J. Kim, “An area efficient multiplier using current-mode quaternary logic technique,” in Proc. 10th IEEE Int. Solid-State Integr. Circuit Technol., Nov. 2010, pp. 403–405.
- W. S. Chu and W. Current, “Current-mode CMOS quaternary multiplier circuit,” Electron. Lett., vol. 31, no. 4, pp. 267–268, 1995.
- K. Current, “Current-mode CMOS multiple-valued logic circuits,” IEEE J. Solid-State Circuits, vol. 29, no. 2, pp. 95–107, Feb. 1994.
- Neil H.E. Weste, Davir Harris,” CMOSVLSI Design: A Circuits and System Perspectives” Addison Wesley – Pearson Education, 3rd Edition, 2004.