AREA-DELAY-POWER EFFICIENT 32*32 VEDIC MULTIPLIER USING HAN-CARLSON ADDER
Author’s Name : K Kalpana | V Monikka | P Sowmiya | A Sabaadhu | S Arunkumar
Volume 01 Issue 04 Year 2014 ISSN No: 2349-252X Page no: 4 – 7
The goal of this venture is to make proficient use of 32*32 bit Vedic Multiplier. Multiplication process plays a substantial role in digital numeric calculation. Vedic mathematics is the antique method of Indian mathematics which has a distinctive technique of calculations based on 16 sutras (Formulae). In this Vedic mathematics Urdhva Triyakabhyam (UT) multiplication method has been used, which fluctuates from general multiplication process. Vedic multiplier is Longley used in incrementing and decrementing the speed and area respectively. In the anticipated technique area, delay is compared. Here, Han-Carlson adder is by means of to reduce area and delay. The procedures coded in Verilog HDL language by using Modelsim and then comparison is supported in Xilinx ISE 8.1 software.
Multiplier,Han-carlson,Vedic Mathematics,UT,VerilogHDL,Ripplecarry Adder
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